LP_SRAM_BASE (reference) in projects: sof-2.7.6

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Searched refs:LP_SRAM_BASE (Results 1 – 12 of 12) sorted by relevance

/sof-2.7.6/src/platform/library/include/platform/lib/
D	memory.h	`72 #define LP_SRAM_BASE 0 macro 149 #define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) 164 #define HEAP_LP_BUFFER_BASE LP_SRAM_BASE`
/sof-2.7.6/src/platform/tigerlake/include/platform/lib/
D	memory.h	`359 #define LP_SRAM_BASE 0xBE800000 macro 363 #define LP_SRAM_ALT_RESET_VEC_BASE LP_SRAM_BASE 376 #define LP_SRAM_START LP_SRAM_BASE 382 #define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) 388 #define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)) 409 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)`
/sof-2.7.6/src/platform/cannonlake/include/platform/lib/
D	memory.h	`349 #define LP_SRAM_BASE 0xBE800000 macro 364 #define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) 378 #define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) 383 #define HEAP_LP_BUFFER_BASE LP_SRAM_BASE 405 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)`
/sof-2.7.6/src/platform/icelake/include/platform/lib/
D	memory.h	`345 #define LP_SRAM_BASE 0xBE800000 macro 350 #define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET) 355 #define HEAP_LP_BUFFER_BASE LP_SRAM_BASE 377 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)`
/sof-2.7.6/src/platform/apollolake/include/platform/lib/
D	memory.h	`363 #define LP_SRAM_BASE 0xBE800000 macro 378 #define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) 389 #define HEAP_LP_BUFFER_BASE LP_SRAM_BASE 410 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)`
/sof-2.7.6/src/platform/suecreek/include/platform/lib/
D	memory.h	`334 #define LP_SRAM_BASE 0xBE800000 macro 349 #define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) 383 #define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE)`
/sof-2.7.6/src/platform/intel/cavs/lib/
D	pm_memory.c	`83 memory_banks_get(ptr, (char *)ptr + size, LP_SRAM_BASE, &start_bank, in cavs_pm_memory_lp_sram_power_gate()`
/sof-2.7.6/src/platform/intel/cavs/
D	lps_wait.c	`44 #define LPSRAM_HEADER_BYPASS_ADDR (LP_SRAM_BASE - SRAM_ALIAS_OFFSET)`
/sof-2.7.6/src/platform/tigerlake/
D	boot_ldr.x.in	`40 org = LP_SRAM_BASE,`
D	tigerlake.x.in	`119 len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)`
/sof-2.7.6/src/platform/icelake/
D	boot_ldr.x.in	`40 org = LP_SRAM_BASE,`
D	icelake.x.in	`106 org = LP_SRAM_BASE,`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
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babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
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babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
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