Searched refs:R5 (Results 1 – 21 of 21) sorted by relevance
15 -enable=MC3R1.R5.916 -enable=MC3R1.R5.117 -enable=MC3R1.R5.618 -enable=MC3R1.R5.719 -enable=MC3R1.R5.8
98 -enable=MC3R1.R5.299 -enable=MC3R1.R5.3100 -enable=MC3R1.R5.4101 -enable=MC3R1.R5.5
10 targets -set -nocase -filter {name =~ "*R5*#0"}17 targets -set -nocase -filter {name =~ "*R5*#0"}
13 MCU, WKUP). This document gives overview of Zephyr running on Cortex R5's58 The J721E does not have a separate flash for the R5 cores. Because of this59 the A72 core has to load the program for the R5 cores to the right memory63 By default the R5's Memory Protection Unit (MPU) only allows for execution of65 carved out for each R5 by Linux. These can be used for IPC (DDR0) and for69 This is the memory mapping from A72 to the memory usable by the R5. Note that70 the R5 cores always see their local ATCM at address 0x00000000 and their BTCM116 Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34)
12 MCU). This document gives overview of Zephyr running on both Cortex R5.16 BeagleY-AI defaults to single-core mode for the R5 subsystem. Changes in that60 The AM67A does not have a separate flash for the R5 core. Because of this61 an A53 core has to load the program for the R5 core to the right memory65 This is the memory mapping from A53 to the memory usable by the R5. Note that66 the R5 core always sees its local TCMA at address 0x00000000 and its TCMB070 the R5. The amount of the allocation can be changed in the Linux device tree.
43 R5, enumerator
14 and aggregating the interrupt sources for ARM Cortex-R5 processor cores.
12 model = "QEMU Cortex-R5";
8 * Two independent R5 cores with their own TCMs (tightly coupled memories)11 This processing unit is based on an ARM Cortex-R5 CPU, it also enables the following devices:51 * Only the first core of the R5 subsystem is supported.53 * The Cortex-R5 and the Cortex-A53 shares the same UART controller, more details below.138 2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)
24 Enable support for AM6X R5 Series.
12 model = "KV260 Cortex-R5";
9 This configuration provides support for an ARM Cortex-R5 CPU and these devices:102 2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)
24 R5 = 5 variable in RegNum76 self.registers[RegNum.R5] = tu[10]
46 set(ICCARM_CPU Cortex-R5)
58 ctx.registers[R5] = esf->extra_info.callee->v2; in z_gdb_entry()
18 * ARM Cortex-R5
88 This option signifies the use of a Cortex-R5 CPU
377 * up to 5 arguments are placed on registers R1 - R5
545 * Xilinx KV260 (Cortex-R5)
920 * :github:`24911` - arch: arm: aarch32: When CPU_HAS_FPU for Cortex-R5 is selected, prep_c.c uses u…
3551 * :github:`49413` - TI-AM62x: Add Zephyr Support for M4 and R5 cores
