Searched refs:CONFIG (Results 1 – 13 of 13) sorted by relevance
120 p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event; in nrf_gpiote_event_enable()127 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk; in nrf_gpiote_event_disable()229 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk); in nrf_gpiote_event_configure()230 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | in nrf_gpiote_event_configure()238 uint32_t final_config = p_reg->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task; in nrf_gpiote_task_enable()239 p_reg->CONFIG[idx] = final_config; in nrf_gpiote_task_enable()246 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk; in nrf_gpiote_task_disable()257 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | in nrf_gpiote_task_configure()261 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | in nrf_gpiote_task_configure()273 p_reg->CONFIG[idx] = (p_reg->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) | in nrf_gpiote_task_force()[all …]
19 p_reg->CRYPTMSTRDMA.CONFIG = (uint32_t)mask; in nrf_cracen_cm_config_indirect_set()25 p_reg->CRYPTMSTRDMA.CONFIG = CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Msk; in nrf_cracen_cm_softreset()27 p_reg->CRYPTMSTRDMA.CONFIG = 0; in nrf_cracen_cm_softreset()
99 p_reg->CONFIG = (uint32_t)p_cfg->parity in nrf_uart_configure()
96 p_reg->CONFIG = (uint32_t)p_cfg->parity in nrf_uarte_configure()
34 uint32_t CONFIG; member60 return (CM_AES_regs.CONFIG & CONFIG_MODE_MASK) >> 8; in nhw_CRACEN_CM_AES_get_mode()64 return ((CM_AES_regs.CONFIG >> 6) & 0x3) | ((CM_AES_regs.CONFIG >> 26) & 0x7);; in nhw_CRACEN_CM_AES_get_KeySel()
273 …if ((CMDMA_regs->CONFIG & CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Msk) == 0) { //Direct mo… in nhw_CRACEN_CM_start()290 …if ((CMDMA_regs->CONFIG & CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Msk) == 0) { //Direct m… in nhw_CRACEN_CM_start()307 if (CMDMA_regs->CONFIG & CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Msk) { in nhw_CRACEN_CM_regw_sideeffects_CONFIG()311 if (CMDMA_regs->CONFIG & CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Msk) { in nhw_CRACEN_CM_regw_sideeffects_CONFIG()314 if (CMDMA_regs->CONFIG & CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Msk) { in nhw_CRACEN_CM_regw_sideeffects_CONFIG()
302 if ((NRF_NVMC_regs[i].CONFIG & NVMC_CONFIG_WEN_Msk) != NVMC_CONFIG_WEN_Een) { \305 __func__, x, i, NRF_NVMC_regs[i].CONFIG); \310 if ((NRF_NVMC_regs[i].CONFIG & NVMC_CONFIG_WEN_Msk) != NVMC_CONFIG_WEN_PEen) { \313 __func__, x, i, NRF_NVMC_regs[i].CONFIG); \497 if ((NRF_NVMC_regs[inst].CONFIG & NVMC_CONFIG_WEN_Msk) == NVMC_CONFIG_WEN_Een) { in nhw_nmvc_write_word()503 if ((NRF_NVMC_regs[inst].CONFIG & NVMC_CONFIG_WEN_Msk) == NVMC_CONFIG_WEN_PEen) { in nhw_nmvc_write_word()512 if ((NRF_NVMC_regs[inst].CONFIG & NVMC_CONFIG_WEN_Msk) != NVMC_CONFIG_WEN_Wen) { in nhw_nmvc_write_word()515 __func__, NRF_NVMC_regs[inst].CONFIG); in nhw_nmvc_write_word()
298 …frame_size = (NRF_UARTE_regs[inst].CONFIG & UARTE_CONFIG_FRAMESIZE_Msk) >> UARTE_CONFIG_FRAMESIZE_… in nhw_uarte_get_frame_size()315 uint32_t CONFIG = NRF_UARTE_regs[inst].CONFIG; in nhw_uarte_one_byte_time() local319 if (CONFIG & UARTE_CONFIG_PARITY_Msk) { in nhw_uarte_one_byte_time()322 if (CONFIG & UARTE_CONFIG_STOP_Msk) { /* Two stop bits */ in nhw_uarte_one_byte_time()385 if ((NRF_UARTE_regs[inst].DMA.RX.MATCH.CONFIG & enable_mask) in nhw_UARTE_Rx_match_check()391 … if (NRF_UARTE_regs[inst].DMA.RX.MATCH.CONFIG & (UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk << i)) { in nhw_UARTE_Rx_match_check()392 NRF_UARTE_regs[inst].DMA.RX.MATCH.CONFIG &= ~enable_mask; in nhw_UARTE_Rx_match_check()423 return (NRF_UARTE_regs[inst].CONFIG & UARTE_CONFIG_HWFC_Msk) != 0; in flow_control_on()476 if (NRF_UARTE_regs[inst].CONFIG & UARTE_CONFIG_ENDIAN_Msk) { //Cut from LSB in nhw_UARTE_process_Rx_byte()727 NRF_UARTE_regs[inst].DMA.RX.MATCH.CONFIG |= UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Msk<<i; in nhw_UARTE_TASK_DMA_RX_ENABLEMATCH()[all …]
347 unsigned int mode = NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_MODE_Msk; in nrf_gpiote_regw_sideeffects_CONFIG()348 unsigned int pin = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_PSEL_Msk) in nrf_gpiote_regw_sideeffects_CONFIG()350 unsigned int port = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_PORT_Msk) in nrf_gpiote_regw_sideeffects_CONFIG()358 unsigned int polarity = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_POLARITY_Msk) in nrf_gpiote_regw_sideeffects_CONFIG()360 unsigned int outinit = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_OUTINIT_Msk) in nrf_gpiote_regw_sideeffects_CONFIG()
71 if (NRF_RNG_regs.CONFIG & RNG_CONFIG_DERCEN_Msk){ //Bias correction enabled in nhw_rng_schedule_next()
184 u_el->tx_line_params.config = NRF_UARTE_regs[inst].CONFIG & CONFIG_RELEVANT_MASK; in tx_sync_line_params()224 if (((NRF_UARTE_regs[inst].CONFIG & CONFIG_RELEVANT_MASK) != u_el->tx_line_params.config) in nhw_ufifo_tx_byte()394 if (( (NRF_UARTE_regs[inst].CONFIG & CONFIG_RELEVANT_MASK) in uf_rx_check_config_match()403 NRF_UARTE_regs[inst].CONFIG, u_el->rx_line_params.config, in uf_rx_check_config_match()
122 NRF_RRAMC_regs[inst].POWER.CONFIG = 0x00000100; in nhw_RRAMC_uicr_init()
2208 …__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configur… member2497 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register … member4835 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register … member6045 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member6316 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
