Searched refs:CC (Results 1 – 25 of 42) sorted by relevance
12
3 set_ifndef(CC gcc)5 find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)9 …message(FATAL_ERROR "Zephyr was unable to find ${CROSS_COMPILE}${CC}. Is the environment misconfig…
3 set_ifndef(CC gcc)5 find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)
18 * CC control and sensing:19 The TCPC implements logic for controlling the CC pin pull-up and pull-down21 present on the CC pin.25 on the CC lines.
7 $(CC) $^ -o $@
4 $(CC) $^ -o $@
174 NRF_GRTC->CC[cmp].CCL = stale; in cntr_cmp_set()181 cntr_l = NRF_GRTC->CC[cmp].CCL; in cntr_cmp_set()185 cntr_h = NRF_GRTC->CC[cmp].CCH; in cntr_cmp_set()
6 $(CC) $^ -lmbedcrypto -o $@
7 $(CC) $^ -o $@ -lpthread
5 $(CC) $^ -o build/$@
135 max = tc->CC[0].reg; in counter_sam0_tc32_relative_alarm()140 tc->CC[1].reg = target; in counter_sam0_tc32_relative_alarm()189 if (alarm_cfg->ticks > tc->CC[0].reg) { in counter_sam0_tc32_set_alarm()204 tc->CC[1].reg = alarm_cfg->ticks; in counter_sam0_tc32_set_alarm()258 tc->CC[0].reg = top_cfg->ticks; in counter_sam0_tc32_set_top_value()300 return tc->CC[0].reg; in counter_sam0_tc32_get_top_value()320 cb(dev, 0, tc->CC[1].reg, data->ch.user_data); in counter_sam0_tc32_isr()373 tc->CC[0].reg = UINT32_MAX; in counter_sam0_tc32_initialize()
7 COMMAND $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/postbuild.sh ${CROSS_COMPILE}${CC}
270 00000010 58 40 00 11 22 33 44 55 66 77 88 99 AA BB CC DD X@.."3DUfw......271 00000020 EE FF 00 11 22 33 44 55 66 77 88 99 AA BB CC DD ...."3DUfw......272 00000030 EE FF 00 11 22 33 44 55 66 77 88 99 AA BB CC DD ...."3DUfw......273 00000040 EE FF 00 11 22 33 44 55 66 77 88 99 AA BB CC DD ...."3DUfw......280 000000B0 BB BB BB BB BB BB BB BB CC CC CC CC CC CC CC CC ................291 00000160 7C 19 19 ED 1F CC C0 49 06 66 53 48 41 32 35 36 |......I.fSHA256311 00000020 02 61 B4 CF 13 CC 70 15 67 30 83 FE A0 D4 2A 19 .a....p.g0....*.325 00000010 EA 96 9E 1D 13 72 1E 4D 35 75 CC D4 C8 01 41 9C .....r.M5u....A.330 00000000 EE F1 FE A6 A8 41 5F CC A6 3A 73 A7 C1 33 B4 78 .....A_..:s..3.x
23 $(CC) -c $(CFLAGS) -MD -Iinclude src/mylib.c -o $(OBJ_DIR)/mylib.o
631 last_pdu_end_us += EVENT_TIMER->CC[HAL_EVENT_TIMER_TRX_END_CC_OFFSET]; in radio_is_done()804 SW_SWITCH_TIMER->CC[cc] - RADIO_EVENTS_PHYEND_DELAY_US); in sw_switch()805 if (delay < SW_SWITCH_TIMER->CC[cc]) { in sw_switch()807 (SW_SWITCH_TIMER->CC[phyend_delay_cc] - delay)); in sw_switch()837 new_cc_s2_value = SW_SWITCH_TIMER->CC[cc]; in sw_switch()921 if (delay < SW_SWITCH_TIMER->CC[cc]) { in sw_switch()924 (SW_SWITCH_TIMER->CC[cc] - delay)); in sw_switch()1200 now_us = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET]; in radio_tmr_isr_set()1450 NRF_GRTC->CC[HAL_CNTR_GRTC_CC_IDX_RADIO].CCL = stale; in radio_tmr_start()1458 cntr_l = NRF_GRTC->CC[HAL_CNTR_GRTC_CC_IDX_RADIO].CCL; in radio_tmr_start()[all …]
33 if (BUS_RegMaskedRead(&cfg->timer->CC[channel].CTRL, in pwm_gecko_set_cycles()55 cfg->timer->CC[channel].CTRL |= (flags & PWM_POLARITY_INVERTED) ? in pwm_gecko_set_cycles()
42 return NRF_TIMER2->CC[0] * ((SystemCoreClock) / CYCLES_PER_SEC); in soc_timing_counter_get()
6 set(CC clang) variable
7 set(CC xcc) variable
11 CC = ${CMAKE_C_COMPILER}
216 | | | | Open | | | Disconnects RCV_FSK from CC LOOP. …218 | | | | Closed | | | Connects RCV_FSK to CC LOOP. …237 | | | | Open | | | Disconnects 249 ohm resistor shunt from CC LOOP. …239 | | | | Closed | | | Connects 249 ohm resistor shunt to CC LOOP. …
