| /Zephyr-latest/subsys/usb/device/class/ |
| D | msc.c | 221 static enum Stage stage; variable
272 stage = MSC_READ_CBW; in msd_state_machine_reset()
292 stage = MSC_WAIT_CSW; in sendCSW()
319 stage = MSC_SEND_CSW; in write()
477 if (!length || (stage != MSC_PROCESS_CBW)) { in thread_memory_read_done()
478 csw.Status = (stage == MSC_PROCESS_CBW) ? in thread_memory_read_done()
480 stage = (stage == MSC_PROCESS_CBW) ? MSC_SEND_CSW : stage; in thread_memory_read_done()
622 stage = MSC_PROCESS_CBW; in CBWDecode()
638 stage = MSC_PROCESS_CBW; in CBWDecode()
657 stage = MSC_PROCESS_CBW; in CBWDecode()
[all …]
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | vector_table_pad.ld | 8 * Padding inserted after the (first-stage) vector table, so that the
16 * first stage vector table.
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| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_common.c | 746 data->stage = CTRL_PIPE_STAGE_SETUP; in udc_enable()
961 return data->stage == CTRL_PIPE_STAGE_DATA_OUT ? true : false; in udc_ctrl_stage_is_data_out()
968 return data->stage == CTRL_PIPE_STAGE_DATA_IN ? true : false; in udc_ctrl_stage_is_data_in()
975 return data->stage == CTRL_PIPE_STAGE_STATUS_OUT ? true : false; in udc_ctrl_stage_is_status_out()
982 return data->stage == CTRL_PIPE_STAGE_STATUS_IN ? true : false; in udc_ctrl_stage_is_status_in()
989 return data->stage == CTRL_PIPE_STAGE_NO_DATA ? true : false; in udc_ctrl_stage_is_no_data()
1015 if (data->stage != CTRL_PIPE_STAGE_SETUP) { in udc_ctrl_update_stage()
1016 LOG_INF("Sequence %u not completed", data->stage); in udc_ctrl_update_stage()
1017 data->stage = CTRL_PIPE_STAGE_SETUP; in udc_ctrl_update_stage()
1049 if (data->stage == CTRL_PIPE_STAGE_DATA_OUT) { in udc_ctrl_update_stage()
[all …]
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.xen | 36 console driver (HVC gets inited on PRE_KERNEL_1 stage).
43 Log output will become available on PRE_KERNEL_1 stage. Requires
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| /Zephyr-latest/drivers/usb/uhc/ |
| D | uhc_virtual.c | 99 if (xfer->stage == UHC_CONTROL_STAGE_SETUP) { in vrt_xfer_control()
114 if (buf != NULL && xfer->stage == UHC_CONTROL_STAGE_DATA) { in vrt_xfer_control()
137 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in vrt_xfer_control()
296 xfer->stage = UHC_CONTROL_STAGE_DATA; in vrt_hrslt_success()
298 xfer->stage = UHC_CONTROL_STAGE_STATUS; in vrt_hrslt_success()
303 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in vrt_hrslt_success()
315 xfer->stage = UHC_CONTROL_STAGE_STATUS; in vrt_hrslt_success()
331 xfer->stage = UHC_CONTROL_STAGE_STATUS; in vrt_hrslt_success()
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| D | uhc_max3421e.c | 322 if (xfer->stage == UHC_CONTROL_STAGE_SETUP) { in max3421e_xfer_control()
338 if (buf != NULL && xfer->stage == UHC_CONTROL_STAGE_DATA) { in max3421e_xfer_control()
343 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in max3421e_xfer_control()
452 xfer->stage = UHC_CONTROL_STAGE_DATA; in max3421e_hrslt_success()
454 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
477 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
506 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
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| /Zephyr-latest/boards/sparkfun/pro_micro_rp2040/ |
| D | sparkfun_pro_micro_rp2040.dts | 32 * the second stage bootloader
41 /* Reserved memory for the second stage bootloader */
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| /Zephyr-latest/tests/subsys/sensing/ |
| D | README.rst | 21 At the current stage, it only supports native_sim.
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| /Zephyr-latest/doc/build/cmake/ |
| D | index.rst | 8 CMake build is done in two stages. The first stage is called
16 **build** stage by executing the generated build scripts. These build scripts
163 :alt: Zephyr's build stage I
174 generated during the configuration phase and the pre-build stage(s)).
178 :alt: Zephyr's build stage II
208 :alt: Zephyr's build stage III
221 :alt: Zephyr's build stage IV
228 The binaries from the previous stage are incomplete, with empty and/or
294 The binary from the previous stage is incomplete, with empty and/or
297 The link from the previous stage is repeated, this time with the missing
[all …]
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| /Zephyr-latest/boards/intel/socfpga/agilex_socdk/doc/ |
| D | index.rst | 52 ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage
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| /Zephyr-latest/boards/wiznet/w5500_evb_pico2/ |
| D | w5500_evb_pico2.dtsi | 85 * the second stage bootloader
94 /* Reserved memory for the second stage bootloader */
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| /Zephyr-latest/boards/seeed/xiao_rp2040/ |
| D | xiao_rp2040.dts | 73 * 2MB of flash minus the 0x100 used for the second stage bootloader
82 /* Reserved memory for the second stage bootloader */
|
| /Zephyr-latest/samples/subsys/sensing/simple/ |
| D | README.rst | 39 At the current stage, it only support native sim.
|
| /Zephyr-latest/boards/wiznet/w5500_evb_pico/ |
| D | w5500_evb_pico.dts | 87 * the second stage bootloader
96 /* Reserved memory for the second stage bootloader */
|
| /Zephyr-latest/doc/services/debugging/ |
| D | symtab.rst | 7 stage that keep tracks of the information about the functions' name and address, for advanced appli…
|
| /Zephyr-latest/cmake/ |
| D | yaml-filter.cmake | 4 # Simple second stage filter for YAML generation, used when generator
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| /Zephyr-latest/modules/hal_rpi_pico/bootloader/ |
| D | CMakeLists.txt | 52 # The second stage bootloader is compiled without kconfig definitions.
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| /Zephyr-latest/share/sysbuild/cmake/modules/ |
| D | sysbuild_images.cmake | 24 # even in the event that one or more image fails configuration stage.
|
| /Zephyr-latest/boards/adafruit/kb2040/ |
| D | adafruit_kb2040.dts | 40 /* Reserved memory for the second stage bootloader */
|
| /Zephyr-latest/boards/waveshare/rp2040_zero/ |
| D | rp2040_zero.dts | 38 /* Reserved memory for the second stage bootloader */
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| /Zephyr-latest/doc/connectivity/bluetooth/api/mesh/ |
| D | dfu.rst | 81 Upload stage
83 phone or gateway (the Initiator). During the Upload stage, the Initiator transfers the firmware
88 time-consuming Distribution stage. Once the firmware has been uploaded to the Distributor, the
89 Initiator may trigger the Distribution stage at any time.
91 Firmware Capability Check stage (optional)
92 Before starting the Distribution stage, the Initiator may optionally check if Target nodes can
96 Distribution stage
235 The Initiator controls the Upload stage of the DFU protocol, and all Distributor side handling of
238 The Distribution stage is controlled by the Distributor, as implemented by the
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| /Zephyr-latest/share/sysbuild/ |
| D | Kconfig | 49 at an experimental implementation stage.
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| /Zephyr-latest/boards/raspberrypi/rpi_pico/ |
| D | rpi_pico-common.dtsi | 73 /* Reserved memory for the second stage bootloader */
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| /Zephyr-latest/cmake/toolchain/arcmwdt/ |
| D | generic.cmake | 27 # On very early stage build system needs to get access to DTC preprocessor.
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.loapic | 54 when the OS starts up, or a previous boot stage has done some IOAPIC
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