Searched refs:Tcc (Results 1 – 13 of 13) sorted by relevance
85 while (((Tcc *)hw)->SYNCBUSY.reg & reg) { in hri_tcc_wait_for_sync()91 return ((Tcc *)hw)->SYNCBUSY.reg & reg; in hri_tcc_is_syncing()97 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_set_COUNT_DITH4_COUNT_bf()104 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_get_COUNT_DITH4_COUNT_bf()113 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_write_COUNT_DITH4_COUNT_bf()116 ((Tcc *)hw)->COUNT.reg = tmp; in hri_tcc_write_COUNT_DITH4_COUNT_bf()123 ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_clear_COUNT_DITH4_COUNT_bf()130 ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_toggle_COUNT_DITH4_COUNT_bf()137 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_read_COUNT_DITH4_COUNT_bf()145 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask); in hri_tcc_set_COUNT_DITH5_COUNT_bf()[all …]
557 #define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */558 #define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */559 #define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */
569 #define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */570 #define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */571 #define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */
1696 } Tcc; typedef