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Searched refs:SCB_CPUID_REVISION_Pos (Results 1 – 17 of 17) sorted by relevance

/loramac-node-latest/src/boards/mcu/saml21/cmsis/
Dcore_cm0.h360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
Dcore_cm0plus.h375 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
376 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
Dcore_sc000.h368 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
369 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
Dcore_cm3.h386 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
Dcore_sc300.h386 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
Dcore_cm4.h433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
434 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
Dcore_cm7.h477 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB … macro
478 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB …
/loramac-node-latest/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_cortex.h484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); in LL_CPUID_GetRevision()
/loramac-node-latest/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_cortex.h484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); in LL_CPUID_GetRevision()
/loramac-node-latest/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_cortex.h435 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); in LL_CPUID_GetRevision()
/loramac-node-latest/src/boards/mcu/stm32/cmsis/
Dcore_cm0.h415 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm0plus.h433 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_sc000.h423 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm3.h455 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_sc300.h457 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm4.h523 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro
Dcore_cm7.h567 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB … macro