Searched refs:PER (Results 1 – 8 of 8) sorted by relevance
430 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ member487 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ member545 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ member601 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ member658 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ member716 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */ member772 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ member829 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ member887 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ member995 uint32_t PER:1; /*!< bit: 4 PER Register Busy */ member[all …]
508 uint32_t PER:1; /*!< bit: 5 Period */ member604 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ member762 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */ member
252 uint32_t PER:1; /*!< bit: 7 Period Busy */ member1354 uint32_t PER:20; /*!< bit: 4..23 Period Value */ member1359 uint32_t PER:19; /*!< bit: 5..23 Period Value */ member1364 uint32_t PER:18; /*!< bit: 6..23 Period Value */ member1368 uint32_t PER:24; /*!< bit: 0..23 Period Value */ member1689 __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ member
70 uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ member
453 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); in hri_tcc_set_PER_DITH4_DITHER_bf()460 tmp = ((Tcc *)hw)->PER.reg; in hri_tcc_get_PER_DITH4_DITHER_bf()469 tmp = ((Tcc *)hw)->PER.reg; in hri_tcc_write_PER_DITH4_DITHER_bf()472 ((Tcc *)hw)->PER.reg = tmp; in hri_tcc_write_PER_DITH4_DITHER_bf()479 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); in hri_tcc_clear_PER_DITH4_DITHER_bf()486 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); in hri_tcc_toggle_PER_DITH4_DITHER_bf()493 tmp = ((Tcc *)hw)->PER.reg; in hri_tcc_read_PER_DITH4_DITHER_bf()501 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask); in hri_tcc_set_PER_DITH4_PER_bf()508 tmp = ((Tcc *)hw)->PER.reg; in hri_tcc_get_PER_DITH4_PER_bf()517 tmp = ((Tcc *)hw)->PER.reg; in hri_tcc_write_PER_DITH4_PER_bf()[all …]
2235 ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); in hri_tc_set_PER_PER_bf()2243 tmp = ((Tc *)hw)->COUNT8.PER.reg; in hri_tc_get_PER_PER_bf()2253 tmp = ((Tc *)hw)->COUNT8.PER.reg; in hri_tc_write_PER_PER_bf()2256 ((Tc *)hw)->COUNT8.PER.reg = tmp; in hri_tc_write_PER_PER_bf()2264 ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); in hri_tc_clear_PER_PER_bf()2272 ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); in hri_tc_toggle_PER_PER_bf()2280 tmp = ((Tc *)hw)->COUNT8.PER.reg; in hri_tc_read_PER_PER_bf()2288 ((Tc *)hw)->COUNT8.PER.reg |= mask; in hri_tc_set_PER_reg()2295 tmp = ((Tc *)hw)->COUNT8.PER.reg; in hri_tc_get_PER_reg()2303 ((Tc *)hw)->COUNT8.PER.reg = data; in hri_tc_write_PER_reg()[all …]
6329 ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); in hri_rtcmode1_set_PER_PER_bf()6337 tmp = ((Rtc *)hw)->MODE1.PER.reg; in hri_rtcmode1_get_PER_PER_bf()6347 tmp = ((Rtc *)hw)->MODE1.PER.reg; in hri_rtcmode1_write_PER_PER_bf()6350 ((Rtc *)hw)->MODE1.PER.reg = tmp; in hri_rtcmode1_write_PER_PER_bf()6358 ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); in hri_rtcmode1_clear_PER_PER_bf()6366 ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); in hri_rtcmode1_toggle_PER_PER_bf()6374 tmp = ((Rtc *)hw)->MODE1.PER.reg; in hri_rtcmode1_read_PER_PER_bf()6382 ((Rtc *)hw)->MODE1.PER.reg |= mask; in hri_rtcmode1_set_PER_reg()6389 tmp = ((Rtc *)hw)->MODE1.PER.reg; in hri_rtcmode1_get_PER_reg()6397 ((Rtc *)hw)->MODE1.PER.reg = data; in hri_rtcmode1_write_PER_reg()[all …]
606 - Optimize radio drivers regarding FSK PER634 …*One of the optional tests is unsuccessful (FSK downlinks PER on Rx1 and Rx2 windows) and is curre…
