/loramac-node-latest/src/boards/mcu/saml21/hri/ |
D | hri_evsys_l21.h | 72 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; in hri_evsys_set_INTEN_OVR0_bit() 77 return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; in hri_evsys_get_INTEN_OVR0_bit() 85 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; in hri_evsys_write_INTEN_OVR0_bit() 96 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; in hri_evsys_set_INTEN_OVR1_bit() 101 return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; in hri_evsys_get_INTEN_OVR1_bit() 109 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; in hri_evsys_write_INTEN_OVR1_bit() 120 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; in hri_evsys_set_INTEN_OVR2_bit() 125 return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; in hri_evsys_get_INTEN_OVR2_bit() 133 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; in hri_evsys_write_INTEN_OVR2_bit() 144 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; in hri_evsys_set_INTEN_OVR3_bit() [all …]
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D | hri_trng_l21.h | 70 ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; in hri_trng_set_INTEN_DATARDY_bit() 75 return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; in hri_trng_get_INTEN_DATARDY_bit() 83 ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; in hri_trng_write_INTEN_DATARDY_bit() 94 ((Trng *)hw)->INTENSET.reg = mask; in hri_trng_set_INTEN_reg() 100 tmp = ((Trng *)hw)->INTENSET.reg; in hri_trng_get_INTEN_reg() 107 return ((Trng *)hw)->INTENSET.reg; in hri_trng_read_INTEN_reg() 112 ((Trng *)hw)->INTENSET.reg = data; in hri_trng_write_INTEN_reg()
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D | hri_rtc_l21.h | 1058 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; in hri_rtcmode2_set_INTEN_PER0_bit() 1063 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; in hri_rtcmode2_get_INTEN_PER0_bit() 1071 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; in hri_rtcmode2_write_INTEN_PER0_bit() 1082 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; in hri_rtcmode2_set_INTEN_PER1_bit() 1087 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; in hri_rtcmode2_get_INTEN_PER1_bit() 1095 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; in hri_rtcmode2_write_INTEN_PER1_bit() 1106 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; in hri_rtcmode2_set_INTEN_PER2_bit() 1111 return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; in hri_rtcmode2_get_INTEN_PER2_bit() 1119 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; in hri_rtcmode2_write_INTEN_PER2_bit() 1130 ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; in hri_rtcmode2_set_INTEN_PER3_bit() [all …]
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D | hri_oscctrl_l21.h | 80 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_set_INTEN_XOSCRDY_bit() 85 return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; in hri_oscctrl_get_INTEN_XOSCRDY_bit() 93 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_write_INTEN_XOSCRDY_bit() 104 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_set_INTEN_OSC16MRDY_bit() 109 …return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_… in hri_oscctrl_get_INTEN_OSC16MRDY_bit() 117 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_write_INTEN_OSC16MRDY_bit() 128 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; in hri_oscctrl_set_INTEN_DFLLRDY_bit() 133 return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; in hri_oscctrl_get_INTEN_DFLLRDY_bit() 141 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; in hri_oscctrl_write_INTEN_DFLLRDY_bit() 152 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; in hri_oscctrl_set_INTEN_DFLLOOB_bit() [all …]
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D | hri_supc_l21.h | 75 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_set_INTEN_BOD33RDY_bit() 80 return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; in hri_supc_get_INTEN_BOD33RDY_bit() 88 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_write_INTEN_BOD33RDY_bit() 99 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; in hri_supc_set_INTEN_BOD33DET_bit() 104 return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; in hri_supc_get_INTEN_BOD33DET_bit() 112 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; in hri_supc_write_INTEN_BOD33DET_bit() 123 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; in hri_supc_set_INTEN_B33SRDY_bit() 128 return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; in hri_supc_get_INTEN_B33SRDY_bit() 136 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; in hri_supc_write_INTEN_B33SRDY_bit() 147 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; in hri_supc_set_INTEN_BOD12RDY_bit() [all …]
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D | hri_dac_l21.h | 87 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_set_INTEN_UNDERRUN0_bit() 92 return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; in hri_dac_get_INTEN_UNDERRUN0_bit() 100 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_write_INTEN_UNDERRUN0_bit() 111 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; in hri_dac_set_INTEN_UNDERRUN1_bit() 116 return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; in hri_dac_get_INTEN_UNDERRUN1_bit() 124 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; in hri_dac_write_INTEN_UNDERRUN1_bit() 135 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; in hri_dac_set_INTEN_EMPTY0_bit() 140 return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; in hri_dac_get_INTEN_EMPTY0_bit() 148 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; in hri_dac_write_INTEN_EMPTY0_bit() 159 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; in hri_dac_set_INTEN_EMPTY1_bit() [all …]
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D | hri_sercom_l21.h | 147 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; in hri_sercomspi_set_INTEN_DRE_bit() 152 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; in hri_sercomspi_get_INTEN_DRE_bit() 160 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; in hri_sercomspi_write_INTEN_DRE_bit() 171 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; in hri_sercomspi_set_INTEN_TXC_bit() 176 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; in hri_sercomspi_get_INTEN_TXC_bit() 184 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; in hri_sercomspi_write_INTEN_TXC_bit() 195 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; in hri_sercomspi_set_INTEN_RXC_bit() 200 return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; in hri_sercomspi_get_INTEN_RXC_bit() 208 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; in hri_sercomspi_write_INTEN_RXC_bit() 219 ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; in hri_sercomspi_set_INTEN_SSL_bit() [all …]
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D | hri_wdt_l21.h | 83 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; in hri_wdt_set_INTEN_EW_bit() 88 return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; in hri_wdt_get_INTEN_EW_bit() 96 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; in hri_wdt_write_INTEN_EW_bit() 107 ((Wdt *)hw)->INTENSET.reg = mask; in hri_wdt_set_INTEN_reg() 113 tmp = ((Wdt *)hw)->INTENSET.reg; in hri_wdt_get_INTEN_reg() 120 return ((Wdt *)hw)->INTENSET.reg; in hri_wdt_read_INTEN_reg() 125 ((Wdt *)hw)->INTENSET.reg = data; in hri_wdt_write_INTEN_reg()
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D | hri_nvmctrl_l21.h | 73 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_set_INTEN_READY_bit() 78 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; in hri_nvmctrl_get_INTEN_READY_bit() 86 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit() 97 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_set_INTEN_ERROR_bit() 102 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; in hri_nvmctrl_get_INTEN_ERROR_bit() 110 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_write_INTEN_ERROR_bit() 121 ((Nvmctrl *)hw)->INTENSET.reg = mask; in hri_nvmctrl_set_INTEN_reg() 128 tmp = ((Nvmctrl *)hw)->INTENSET.reg; in hri_nvmctrl_get_INTEN_reg() 135 return ((Nvmctrl *)hw)->INTENSET.reg; in hri_nvmctrl_read_INTEN_reg() 140 ((Nvmctrl *)hw)->INTENSET.reg = data; in hri_nvmctrl_write_INTEN_reg()
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D | hri_osc32kctrl_l21.h | 72 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit() 77 …return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_… in hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit() 85 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit() 96 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_set_INTEN_OSC32KRDY_bit() 101 …return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_OSC32KRDY) >> OSC32KCTRL_INTENSET_O… in hri_osc32kctrl_get_INTEN_OSC32KRDY_bit() 109 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_write_INTEN_OSC32KRDY_bit() 120 ((Osc32kctrl *)hw)->INTENSET.reg = mask; in hri_osc32kctrl_set_INTEN_reg() 127 tmp = ((Osc32kctrl *)hw)->INTENSET.reg; in hri_osc32kctrl_get_INTEN_reg() 134 return ((Osc32kctrl *)hw)->INTENSET.reg; in hri_osc32kctrl_read_INTEN_reg() 139 ((Osc32kctrl *)hw)->INTENSET.reg = data; in hri_osc32kctrl_write_INTEN_reg()
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D | hri_aes_l21.h | 78 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; in hri_aes_set_INTEN_ENCCMP_bit() 83 return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; in hri_aes_get_INTEN_ENCCMP_bit() 91 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; in hri_aes_write_INTEN_ENCCMP_bit() 102 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; in hri_aes_set_INTEN_GFMCMP_bit() 107 return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; in hri_aes_get_INTEN_GFMCMP_bit() 115 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; in hri_aes_write_INTEN_GFMCMP_bit() 126 ((Aes *)hw)->INTENSET.reg = mask; in hri_aes_set_INTEN_reg() 132 tmp = ((Aes *)hw)->INTENSET.reg; in hri_aes_get_INTEN_reg() 139 return ((Aes *)hw)->INTENSET.reg; in hri_aes_read_INTEN_reg() 144 ((Aes *)hw)->INTENSET.reg = data; in hri_aes_write_INTEN_reg()
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D | hri_ac_l21.h | 88 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; in hri_ac_set_INTEN_COMP0_bit() 93 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; in hri_ac_get_INTEN_COMP0_bit() 101 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; in hri_ac_write_INTEN_COMP0_bit() 112 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; in hri_ac_set_INTEN_COMP1_bit() 117 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; in hri_ac_get_INTEN_COMP1_bit() 125 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; in hri_ac_write_INTEN_COMP1_bit() 136 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; in hri_ac_set_INTEN_WIN0_bit() 141 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; in hri_ac_get_INTEN_WIN0_bit() 149 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; in hri_ac_write_INTEN_WIN0_bit() 160 ((Ac *)hw)->INTENSET.reg = mask; in hri_ac_set_INTEN_reg() [all …]
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D | hri_pm_l21.h | 72 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; in hri_pm_set_INTEN_PLRDY_bit() 77 return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; in hri_pm_get_INTEN_PLRDY_bit() 85 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; in hri_pm_write_INTEN_PLRDY_bit() 96 ((Pm *)hw)->INTENSET.reg = mask; in hri_pm_set_INTEN_reg() 102 tmp = ((Pm *)hw)->INTENSET.reg; in hri_pm_get_INTEN_reg() 109 return ((Pm *)hw)->INTENSET.reg; in hri_pm_read_INTEN_reg() 114 ((Pm *)hw)->INTENSET.reg = data; in hri_pm_write_INTEN_reg()
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D | hri_usb_l21.h | 1718 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; in hri_usbhost_set_INTEN_HSOF_bit() 1723 return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; in hri_usbhost_get_INTEN_HSOF_bit() 1731 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; in hri_usbhost_write_INTEN_HSOF_bit() 1742 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; in hri_usbhost_set_INTEN_RST_bit() 1747 return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; in hri_usbhost_get_INTEN_RST_bit() 1755 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; in hri_usbhost_write_INTEN_RST_bit() 1766 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; in hri_usbhost_set_INTEN_WAKEUP_bit() 1771 return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; in hri_usbhost_get_INTEN_WAKEUP_bit() 1779 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; in hri_usbhost_write_INTEN_WAKEUP_bit() 1790 ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; in hri_usbhost_set_INTEN_DNRSM_bit() [all …]
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D | hri_pac_l21.h | 79 ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; in hri_pac_set_INTEN_ERR_bit() 84 return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; in hri_pac_get_INTEN_ERR_bit() 92 ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; in hri_pac_write_INTEN_ERR_bit() 103 ((Pac *)hw)->INTENSET.reg = mask; in hri_pac_set_INTEN_reg() 109 tmp = ((Pac *)hw)->INTENSET.reg; in hri_pac_get_INTEN_reg() 116 return ((Pac *)hw)->INTENSET.reg; in hri_pac_read_INTEN_reg() 121 ((Pac *)hw)->INTENSET.reg = data; in hri_pac_write_INTEN_reg()
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D | hri_adc_l21.h | 97 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; in hri_adc_set_INTEN_RESRDY_bit() 102 return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; in hri_adc_get_INTEN_RESRDY_bit() 110 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; in hri_adc_write_INTEN_RESRDY_bit() 121 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; in hri_adc_set_INTEN_OVERRUN_bit() 126 return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; in hri_adc_get_INTEN_OVERRUN_bit() 134 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; in hri_adc_write_INTEN_OVERRUN_bit() 145 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; in hri_adc_set_INTEN_WINMON_bit() 150 return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; in hri_adc_get_INTEN_WINMON_bit() 158 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; in hri_adc_write_INTEN_WINMON_bit() 169 ((Adc *)hw)->INTENSET.reg = mask; in hri_adc_set_INTEN_reg() [all …]
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D | hri_tc_l21.h | 768 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; in hri_tc_set_INTEN_OVF_bit() 773 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; in hri_tc_get_INTEN_OVF_bit() 781 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; in hri_tc_write_INTEN_OVF_bit() 792 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; in hri_tc_set_INTEN_ERR_bit() 797 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; in hri_tc_get_INTEN_ERR_bit() 805 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; in hri_tc_write_INTEN_ERR_bit() 816 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; in hri_tc_set_INTEN_MC0_bit() 821 return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; in hri_tc_get_INTEN_MC0_bit() 829 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; in hri_tc_write_INTEN_MC0_bit() 840 ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; in hri_tc_set_INTEN_MC1_bit() [all …]
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D | hri_eic_l21.h | 85 ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); in hri_eic_set_INTEN_EXTINT_bf() 91 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_get_INTEN_EXTINT_bf() 99 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_read_INTEN_EXTINT_bf() 106 ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); in hri_eic_write_INTEN_EXTINT_bf() 117 ((Eic *)hw)->INTENSET.reg = mask; in hri_eic_set_INTEN_reg() 123 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_get_INTEN_reg() 130 return ((Eic *)hw)->INTENSET.reg; in hri_eic_read_INTEN_reg() 135 ((Eic *)hw)->INTENSET.reg = data; in hri_eic_write_INTEN_reg()
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D | hri_tcc_l21.h | 2636 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; in hri_tcc_set_INTEN_OVF_bit() 2641 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; in hri_tcc_get_INTEN_OVF_bit() 2649 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; in hri_tcc_write_INTEN_OVF_bit() 2660 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; in hri_tcc_set_INTEN_TRG_bit() 2665 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; in hri_tcc_get_INTEN_TRG_bit() 2673 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; in hri_tcc_write_INTEN_TRG_bit() 2684 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; in hri_tcc_set_INTEN_CNT_bit() 2689 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; in hri_tcc_get_INTEN_CNT_bit() 2697 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; in hri_tcc_write_INTEN_CNT_bit() 2708 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; in hri_tcc_set_INTEN_ERR_bit() [all …]
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/loramac-node-latest/src/boards/mcu/saml21/saml21b/include/component/ |
D | trng.h | 162 …__IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
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D | tc.h | 752 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member 778 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member 802 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
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D | sercom.h | 1352 …__IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enabl… member 1374 …__IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enabl… member 1396 …__IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable… member 1421 …__IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Ena… member
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D | pm.h | 265 …__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set… member
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D | osc32kctrl.h | 271 …__IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set… member
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D | aes.h | 304 …__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set… member
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