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Searched refs:INTENCLR (Results 1 – 25 of 42) sorted by relevance

12

/loramac-node-latest/src/boards/mcu/saml21/hri/
Dhri_evsys_l21.h83 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; in hri_evsys_write_INTEN_OVR0_bit()
91 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; in hri_evsys_clear_INTEN_OVR0_bit()
107 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; in hri_evsys_write_INTEN_OVR1_bit()
115 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; in hri_evsys_clear_INTEN_OVR1_bit()
131 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; in hri_evsys_write_INTEN_OVR2_bit()
139 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; in hri_evsys_clear_INTEN_OVR2_bit()
155 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; in hri_evsys_write_INTEN_OVR3_bit()
163 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; in hri_evsys_clear_INTEN_OVR3_bit()
179 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; in hri_evsys_write_INTEN_OVR4_bit()
187 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; in hri_evsys_clear_INTEN_OVR4_bit()
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Dhri_rtc_l21.h1069 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; in hri_rtcmode2_write_INTEN_PER0_bit()
1077 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; in hri_rtcmode2_clear_INTEN_PER0_bit()
1093 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; in hri_rtcmode2_write_INTEN_PER1_bit()
1101 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; in hri_rtcmode2_clear_INTEN_PER1_bit()
1117 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; in hri_rtcmode2_write_INTEN_PER2_bit()
1125 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; in hri_rtcmode2_clear_INTEN_PER2_bit()
1141 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; in hri_rtcmode2_write_INTEN_PER3_bit()
1149 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; in hri_rtcmode2_clear_INTEN_PER3_bit()
1165 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; in hri_rtcmode2_write_INTEN_PER4_bit()
1173 ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; in hri_rtcmode2_clear_INTEN_PER4_bit()
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Dhri_trng_l21.h81 ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; in hri_trng_write_INTEN_DATARDY_bit()
89 ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; in hri_trng_clear_INTEN_DATARDY_bit()
113 ((Trng *)hw)->INTENCLR.reg = ~data; in hri_trng_write_INTEN_reg()
118 ((Trng *)hw)->INTENCLR.reg = mask; in hri_trng_clear_INTEN_reg()
Dhri_oscctrl_l21.h91 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_write_INTEN_XOSCRDY_bit()
99 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_clear_INTEN_XOSCRDY_bit()
115 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_write_INTEN_OSC16MRDY_bit()
123 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_clear_INTEN_OSC16MRDY_bit()
139 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; in hri_oscctrl_write_INTEN_DFLLRDY_bit()
147 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; in hri_oscctrl_clear_INTEN_DFLLRDY_bit()
163 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; in hri_oscctrl_write_INTEN_DFLLOOB_bit()
171 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; in hri_oscctrl_clear_INTEN_DFLLOOB_bit()
187 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; in hri_oscctrl_write_INTEN_DFLLLCKF_bit()
195 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; in hri_oscctrl_clear_INTEN_DFLLLCKF_bit()
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Dhri_supc_l21.h86 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_write_INTEN_BOD33RDY_bit()
94 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_clear_INTEN_BOD33RDY_bit()
110 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; in hri_supc_write_INTEN_BOD33DET_bit()
118 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; in hri_supc_clear_INTEN_BOD33DET_bit()
134 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; in hri_supc_write_INTEN_B33SRDY_bit()
142 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; in hri_supc_clear_INTEN_B33SRDY_bit()
158 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; in hri_supc_write_INTEN_BOD12RDY_bit()
166 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; in hri_supc_clear_INTEN_BOD12RDY_bit()
182 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; in hri_supc_write_INTEN_BOD12DET_bit()
190 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; in hri_supc_clear_INTEN_BOD12DET_bit()
[all …]
Dhri_dac_l21.h98 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_write_INTEN_UNDERRUN0_bit()
106 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_clear_INTEN_UNDERRUN0_bit()
122 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; in hri_dac_write_INTEN_UNDERRUN1_bit()
130 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; in hri_dac_clear_INTEN_UNDERRUN1_bit()
146 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; in hri_dac_write_INTEN_EMPTY0_bit()
154 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; in hri_dac_clear_INTEN_EMPTY0_bit()
170 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; in hri_dac_write_INTEN_EMPTY1_bit()
178 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; in hri_dac_clear_INTEN_EMPTY1_bit()
202 ((Dac *)hw)->INTENCLR.reg = ~data; in hri_dac_write_INTEN_reg()
207 ((Dac *)hw)->INTENCLR.reg = mask; in hri_dac_clear_INTEN_reg()
Dhri_sercom_l21.h158 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; in hri_sercomspi_write_INTEN_DRE_bit()
166 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; in hri_sercomspi_clear_INTEN_DRE_bit()
182 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; in hri_sercomspi_write_INTEN_TXC_bit()
190 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; in hri_sercomspi_clear_INTEN_TXC_bit()
206 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; in hri_sercomspi_write_INTEN_RXC_bit()
214 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; in hri_sercomspi_clear_INTEN_RXC_bit()
230 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; in hri_sercomspi_write_INTEN_SSL_bit()
238 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; in hri_sercomspi_clear_INTEN_SSL_bit()
254 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; in hri_sercomspi_write_INTEN_ERROR_bit()
262 ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; in hri_sercomspi_clear_INTEN_ERROR_bit()
[all …]
Dhri_wdt_l21.h94 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; in hri_wdt_write_INTEN_EW_bit()
102 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; in hri_wdt_clear_INTEN_EW_bit()
126 ((Wdt *)hw)->INTENCLR.reg = ~data; in hri_wdt_write_INTEN_reg()
131 ((Wdt *)hw)->INTENCLR.reg = mask; in hri_wdt_clear_INTEN_reg()
Dhri_nvmctrl_l21.h84 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()
92 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_clear_INTEN_READY_bit()
108 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_write_INTEN_ERROR_bit()
116 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_clear_INTEN_ERROR_bit()
141 ((Nvmctrl *)hw)->INTENCLR.reg = ~data; in hri_nvmctrl_write_INTEN_reg()
146 ((Nvmctrl *)hw)->INTENCLR.reg = mask; in hri_nvmctrl_clear_INTEN_reg()
Dhri_osc32kctrl_l21.h83 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit()
91 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit()
107 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_write_INTEN_OSC32KRDY_bit()
115 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_clear_INTEN_OSC32KRDY_bit()
140 ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; in hri_osc32kctrl_write_INTEN_reg()
145 ((Osc32kctrl *)hw)->INTENCLR.reg = mask; in hri_osc32kctrl_clear_INTEN_reg()
Dhri_aes_l21.h89 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; in hri_aes_write_INTEN_ENCCMP_bit()
97 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; in hri_aes_clear_INTEN_ENCCMP_bit()
113 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; in hri_aes_write_INTEN_GFMCMP_bit()
121 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; in hri_aes_clear_INTEN_GFMCMP_bit()
145 ((Aes *)hw)->INTENCLR.reg = ~data; in hri_aes_write_INTEN_reg()
150 ((Aes *)hw)->INTENCLR.reg = mask; in hri_aes_clear_INTEN_reg()
Dhri_ac_l21.h99 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; in hri_ac_write_INTEN_COMP0_bit()
107 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; in hri_ac_clear_INTEN_COMP0_bit()
123 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; in hri_ac_write_INTEN_COMP1_bit()
131 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; in hri_ac_clear_INTEN_COMP1_bit()
147 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; in hri_ac_write_INTEN_WIN0_bit()
155 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; in hri_ac_clear_INTEN_WIN0_bit()
179 ((Ac *)hw)->INTENCLR.reg = ~data; in hri_ac_write_INTEN_reg()
184 ((Ac *)hw)->INTENCLR.reg = mask; in hri_ac_clear_INTEN_reg()
Dhri_pm_l21.h83 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; in hri_pm_write_INTEN_PLRDY_bit()
91 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; in hri_pm_clear_INTEN_PLRDY_bit()
115 ((Pm *)hw)->INTENCLR.reg = ~data; in hri_pm_write_INTEN_reg()
120 ((Pm *)hw)->INTENCLR.reg = mask; in hri_pm_clear_INTEN_reg()
Dhri_usb_l21.h1729 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; in hri_usbhost_write_INTEN_HSOF_bit()
1737 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; in hri_usbhost_clear_INTEN_HSOF_bit()
1753 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; in hri_usbhost_write_INTEN_RST_bit()
1761 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; in hri_usbhost_clear_INTEN_RST_bit()
1777 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; in hri_usbhost_write_INTEN_WAKEUP_bit()
1785 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; in hri_usbhost_clear_INTEN_WAKEUP_bit()
1801 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; in hri_usbhost_write_INTEN_DNRSM_bit()
1809 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; in hri_usbhost_clear_INTEN_DNRSM_bit()
1825 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; in hri_usbhost_write_INTEN_UPRSM_bit()
1833 ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; in hri_usbhost_clear_INTEN_UPRSM_bit()
[all …]
Dhri_tc_l21.h779 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; in hri_tc_write_INTEN_OVF_bit()
787 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; in hri_tc_clear_INTEN_OVF_bit()
803 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; in hri_tc_write_INTEN_ERR_bit()
811 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; in hri_tc_clear_INTEN_ERR_bit()
827 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; in hri_tc_write_INTEN_MC0_bit()
835 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; in hri_tc_clear_INTEN_MC0_bit()
851 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; in hri_tc_write_INTEN_MC1_bit()
859 ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; in hri_tc_clear_INTEN_MC1_bit()
883 ((Tc *)hw)->COUNT8.INTENCLR.reg = ~data; in hri_tc_write_INTEN_reg()
888 ((Tc *)hw)->COUNT8.INTENCLR.reg = mask; in hri_tc_clear_INTEN_reg()
Dhri_adc_l21.h108 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; in hri_adc_write_INTEN_RESRDY_bit()
116 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; in hri_adc_clear_INTEN_RESRDY_bit()
132 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; in hri_adc_write_INTEN_OVERRUN_bit()
140 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; in hri_adc_clear_INTEN_OVERRUN_bit()
156 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; in hri_adc_write_INTEN_WINMON_bit()
164 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; in hri_adc_clear_INTEN_WINMON_bit()
188 ((Adc *)hw)->INTENCLR.reg = ~data; in hri_adc_write_INTEN_reg()
193 ((Adc *)hw)->INTENCLR.reg = mask; in hri_adc_clear_INTEN_reg()
Dhri_pac_l21.h90 ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; in hri_pac_write_INTEN_ERR_bit()
98 ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; in hri_pac_clear_INTEN_ERR_bit()
122 ((Pac *)hw)->INTENCLR.reg = ~data; in hri_pac_write_INTEN_reg()
127 ((Pac *)hw)->INTENCLR.reg = mask; in hri_pac_clear_INTEN_reg()
Dhri_tcc_l21.h2647 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; in hri_tcc_write_INTEN_OVF_bit()
2655 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; in hri_tcc_clear_INTEN_OVF_bit()
2671 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; in hri_tcc_write_INTEN_TRG_bit()
2679 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; in hri_tcc_clear_INTEN_TRG_bit()
2695 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; in hri_tcc_write_INTEN_CNT_bit()
2703 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; in hri_tcc_clear_INTEN_CNT_bit()
2719 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; in hri_tcc_write_INTEN_ERR_bit()
2727 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; in hri_tcc_clear_INTEN_ERR_bit()
2743 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; in hri_tcc_write_INTEN_UFS_bit()
2751 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; in hri_tcc_clear_INTEN_UFS_bit()
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/loramac-node-latest/src/boards/mcu/saml21/saml21b/include/component/
Dtrng.h161 …__IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle… member
Dtc.h751 …__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle… member
777 …__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle… member
801 …__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle… member
Dsercom.h1350 …__IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enabl… member
1372 …__IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enabl… member
1394 …__IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable… member
1419 …__IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Ena… member
Dosc32kctrl.h270 …__IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Cle… member
Dpm.h264 …__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Cle… member
Daes.h303 …__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Cle… member
Dwdt.h288 …__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clea… member

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