Searched refs:EVCPUSEL0 (Results 1 – 2 of 2) sorted by relevance
1454 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH0_Msk; in hri_tal_set_EVCPUSEL0_CH0_bit()1461 tmp = ((Tal *)hw)->EVCPUSEL0.reg; in hri_tal_get_EVCPUSEL0_CH0_bit()1470 tmp = ((Tal *)hw)->EVCPUSEL0.reg; in hri_tal_write_EVCPUSEL0_CH0_bit()1473 ((Tal *)hw)->EVCPUSEL0.reg = tmp; in hri_tal_write_EVCPUSEL0_CH0_bit()1480 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH0_Msk; in hri_tal_clear_EVCPUSEL0_CH0_bit()1487 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH0_Msk; in hri_tal_toggle_EVCPUSEL0_CH0_bit()1494 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH1_Msk; in hri_tal_set_EVCPUSEL0_CH1_bit()1501 tmp = ((Tal *)hw)->EVCPUSEL0.reg; in hri_tal_get_EVCPUSEL0_CH1_bit()1510 tmp = ((Tal *)hw)->EVCPUSEL0.reg; in hri_tal_write_EVCPUSEL0_CH1_bit()1513 ((Tal *)hw)->EVCPUSEL0.reg = tmp; in hri_tal_write_EVCPUSEL0_CH1_bit()[all …]
872 …__IO TAL_EVCPUSEL0_Type EVCPUSEL0; /**< \brief Offset: 0x48 (R/W 32) EVSYS Channel Interr… member
