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Searched refs:SCB (Results 1 – 25 of 32) sorted by relevance

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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_cortex.h329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
411 SET_BIT(SCB->SHCSR, Fault); in LL_HANDLER_EnableFault()
426 CLEAR_BIT(SCB->SHCSR, Fault); in LL_HANDLER_DisableFault()
444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); in LL_CPUID_GetImplementer()
454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); in LL_CPUID_GetVariant()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_cortex.h329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
411 SET_BIT(SCB->SHCSR, Fault); in LL_HANDLER_EnableFault()
426 CLEAR_BIT(SCB->SHCSR, Fault); in LL_HANDLER_DisableFault()
444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); in LL_CPUID_GetImplementer()
454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); in LL_CPUID_GetVariant()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_pwr.c472 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
518 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
534 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
554 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
576 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
589 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_pwr.c496 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSLEEPMode()
558 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
575 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
598 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTANDBYMode()
619 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
632 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
645 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
658 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_cortex.h318 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
329 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
353 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
365 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
377 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
395 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); in LL_CPUID_GetImplementer()
405 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); in LL_CPUID_GetVariant()
415 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); in LL_CPUID_GetArchitecture()
425 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); in LL_CPUID_GetParNo()
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr.c491 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
579 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
629 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
642 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
Dstm32l4xx_hal_pwr_ex.c1184 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP0Mode()
1201 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP0Mode()
1235 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode()
1252 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode()
1287 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode()
1304 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode()
1327 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSHUTDOWNMode()
/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/
Dcore_cm7.h1751 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1809 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1814 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1825 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in NVIC_GetPriorityGrouping()
1910 …SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS… in NVIC_SetPriority()
1933 … return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in NVIC_GetPriority()
2002 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
2003 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
2036 mvfr0 = SCB->MVFR0; in SCB_GetFPUType()
2078 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
[all …]
Dcore_cm0.h587 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
692 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
717 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in NVIC_GetPriority()
734 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
Dcore_cm0plus.h699 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
808 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
833 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in NVIC_GetPriority()
850 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
Dcore_sc000.h711 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
820 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
845 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in NVIC_GetPriority()
862 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
Dcore_cm3.h1374 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1427 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1432 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1443 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in NVIC_GetPriorityGrouping()
1528 …SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)… in NVIC_SetPriority()
1551 … return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in NVIC_GetPriority()
1620 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
1621 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
Dcore_sc300.h1356 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1409 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1414 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1425 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in NVIC_GetPriorityGrouping()
1510 …SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)… in NVIC_SetPriority()
1533 … return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in NVIC_GetPriority()
1602 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
1603 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm7.h1597 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1654 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1659 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1671 …return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority group… in NVIC_GetPriorityGrouping()
1767 …SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pr… in NVIC_SetPriority()
1788 …return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get pri… in NVIC_GetPriority()
1856 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
1857 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
1888 SCB->ICIALLU = 0; // invalidate I-Cache in SCB_EnableICache()
1889 SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache in SCB_EnableICache()
[all …]
Dcore_cm0.h503 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
614 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
637 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BIT… in NVIC_GetPriority()
651 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
Dcore_cm0plus.h610 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
725 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
748 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BIT… in NVIC_GetPriority()
762 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
Dcore_sc000.h630 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
745 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | in NVIC_SetPriority()
768 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BIT… in NVIC_GetPriority()
782 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
Dcore_cm3.h1264 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1316 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1321 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1333 …return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority group… in NVIC_GetPriorityGrouping()
1428 …SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pri… in NVIC_SetPriority()
1449 …return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get prio… in NVIC_GetPriority()
1517 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
1518 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
Dcore_sc300.h1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1296 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1301 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1313 …return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority group… in NVIC_GetPriorityGrouping()
1408 …SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pri… in NVIC_SetPriority()
1429 …return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get prio… in NVIC_GetPriority()
1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
Dcore_cm4.h1410 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1467 …reg_value = SCB->AIRCR; /* read old register c… in NVIC_SetPriorityGrouping()
1472 SCB->AIRCR = reg_value; in NVIC_SetPriorityGrouping()
1484 …return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority group… in NVIC_GetPriorityGrouping()
1580 …SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Pri… in NVIC_SetPriority()
1601 …return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get prio… in NVIC_GetPriority()
1669 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | in NVIC_SystemReset()
1670 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in NVIC_SystemReset()
/loramac-node-3.4.0/src/boards/NucleoL476/cmsis/
Dsystem_stm32l4xx.c200 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ in SystemInit()
224 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ in SystemInit()
226 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ in SystemInit()
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dsystem_stm32l0xx.c176 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ in SystemInit()
178 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ in SystemInit()
/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dsystem_stm32l0xx.c176 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ in SystemInit()
178 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ in SystemInit()
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dsystem_stm32l0xx.c176 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ in SystemInit()
178 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ in SystemInit()
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dsystem_stm32l1xx.c183 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ in SystemInit()
185 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ in SystemInit()

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