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Searched refs:CSSELR (Results 1 – 2 of 2) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/
Dcore_cm7.h525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2130 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_EnableDCache()
2168 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_DisableDCache()
2205 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_InvalidateDCache()
2240 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanDCache()
2275 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm7.h435 …__IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register … member