Searched refs:CHANNEL (Results 1 – 8 of 8) sorted by relevance
71 config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); in mcux_qtmr_pwm_set_cycles()76 config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()77 config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()80 config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()81 config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()83 reg = config->base->CHANNEL[channel].CSCTRL; in mcux_qtmr_pwm_set_cycles()89 config->base->CHANNEL[channel].CSCTRL = reg; in mcux_qtmr_pwm_set_cycles()91 reg = config->base->CHANNEL[channel].CTRL; in mcux_qtmr_pwm_set_cycles()104 config->base->CHANNEL[channel].CTRL = reg; in mcux_qtmr_pwm_set_cycles()
73 base->CHANNEL[channel_id].INTVAL = MRT_CHANNEL_INTVAL_LOAD(1); in nxp_mrt_stop()93 base->CHANNEL[channel_id].INTVAL = data->top; in nxp_mrt_start()106 *ticks = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK; in nxp_mrt_get_value()120 bool active = base->CHANNEL[channel_id].STAT & MRT_CHANNEL_STAT_RUN_MASK; in nxp_mrt_set_top_value()121 uint32_t current_val = base->CHANNEL[channel_id].TIMER & MRT_CHANNEL_TIMER_VALUE_MASK; in nxp_mrt_set_top_value()152 base->CHANNEL[channel_id].INTVAL = MRT_CHANNEL_INTVAL_IVALUE(cfg->ticks) | in nxp_mrt_set_top_value()157 base->CHANNEL[channel_id].INTVAL & MRT_CHANNEL_INTVAL_IVALUE_MASK); in nxp_mrt_set_top_value()168 return base->CHANNEL[channel_id].INTVAL & MRT_CHANNEL_INTVAL_IVALUE_MASK; in nxp_mrt_get_top_value()177 return base->CHANNEL[channel_id].STAT & MRT_CHANNEL_STAT_INTFLAG_MASK; in nxp_mrt_get_pending_int()235 base->CHANNEL[i].CTRL = MRT_CHANNEL_CTRL_INTEN_MASK; in nxp_mrt_init()[all …]
178 config->base->CHANNEL[config->channel].COMP1 = ticks; in mcux_qtmr_set_alarm()223 if ((config->base->CHANNEL[config->channel].CTRL & TMR_CTRL_DIR_MASK) != 0U) { in mcux_qtmr_set_top_value()225 config->base->CHANNEL[config->channel].CNTR = UINT16_MAX; in mcux_qtmr_set_top_value()228 config->base->CHANNEL[config->channel].CNTR = 0; in mcux_qtmr_set_top_value()
66 return (config->base->CHANNEL[channel].LDVAL + 1); in nxp_pit_get_top_value()117 if (config->base->CHANNEL[channel].TCTRL & PIT_TCTRL_TEN_MASK) { in nxp_pit_set_top_value()
61 regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line); in rv32m1_intmux_irq_enable()70 regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line); in rv32m1_intmux_irq_disable()79 if (regs->CHANNEL[i].CHn_IER_31_0) { in rv32m1_intmux_get_state()94 if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) { in rv32m1_intmux_get_line_state()114 uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2); in rv32m1_intmux_isr()171 regs->CHANNEL[i].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK; in rv32m1_intmux_init()
57 #define CHANNEL(ch) ((ch & 0x7) << 4) macro70 [0] = START | CHANNEL(CH_Z1) | POWER_ON,71 [2] = START | CHANNEL(CH_Z2) | POWER_ON,72 [4] = START | CHANNEL(CH_X) | POWER_ON,73 [6] = START | CHANNEL(CH_Y) | POWER_OFF,
127 ier = INTMUX->CHANNEL[channel].CHn_IER_31_0 & BIT(line); in arch_irq_is_enabled()
526 DEV_BASE(dev)->CHANNEL[ChannelToDisable].CFG &= in dma_mcux_lpc_configure()545 DEV_BASE(dev)->CHANNEL[config->linked_channel].CFG |= in dma_mcux_lpc_configure()567 DEV_BASE(dev)->CHANNEL[ChannelToDisable].CFG &= in dma_mcux_lpc_configure()711 p_handle->base->CHANNEL[p_handle->channel].CFG = cfg_reg; in dma_mcux_lpc_configure()
