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/hal_xtensa-latest/src/hal/
Ddebug_hndlr.S86 bbci.l a3, DEBUGCAUSE_ICOUNT_SHIFT, 1f // ICOUNT trap?
96 1: bbci.l a3, DEBUGCAUSE_IBREAK_SHIFT, 1f // IBREAK match?
104 1: bbci.l a3, DEBUGCAUSE_DBREAK_SHIFT, 1f // DBREAK match?
113 1: bbci.l a3, DEBUGCAUSE_BREAK_SHIFT, 1f // BREAK instruction?
123 1: bbci.l a3, DEBUGCAUSE_BREAKN_SHIFT, 1f // BREAK.N instruction?
129 1: bbci.l a3, DEBUGCAUSE_DEBUGINT_SHIFT, 1f // debug interrupt?
Dmem_ecc_parity.S100 bbsi.l a4, 4, 1f // branch if correctable error requested
124 bbsi.l a8, MESR_ERRTEST_SHIFT, .Lproceed // already in test mode?
126 bbci.l a8, MESR_ERRENAB_SHIFT, 1f
130 bbci.l a9, MESR_RCE_SHIFT, .Lproceed // we likely restored a lost RCE, just keep it
142 bbci.l a9, MESR_ERRENAB_SHIFT, 1f
161 bbci.l a4, 2, .L_inject_local // branch if injecting to local memory
162 bbsi.l a4, 1, .L_inject_icache // branch if injecting to icache
164 bbci.l a4, 0, .L_inject_local // branch if injecting to dcache data
190 bbci.l a4, 0, .L_inject_icw // branch if injecting to icache data
255 bbsi.l a8, MESR_ERRTEST_SHIFT, 2f // was already in test mode
[all …]
Dwindowspill_asm.S211 bbsi.l a2, 0, .Lspill4 // if next start bit is set, it's a call4
212 bbsi.l a2, 1, .Lspill8 // if 2nd next bit set, it's a call8
213 bbsi.l a2, 2, .Lspill12 // if 3rd next bit set, it's a call12
321 bbsi.l a2, WSBITS-1, 2f // branch if current WINDOWBASE==original
324 bbci.l a2, WSBITS-1, 1b // repeat until ms start bit set
Dmemcopy.S32 # define BL(b,l) b argument
34 # define BL(b,l) l argument
227 bbci.l a4, 3, .L2
236 bbci.l a4, 2, .L3
367 bbci.l a4, 3, .L12
379 bbci.l a4, 2, .L13
Dcache_asm.S105 7: j.l xthal_dcache_region_\name + ABI_ENTRY_MINSIZE, a4
170 7: j.l xthal_icache_region_\name + ABI_ENTRY_MINSIZE, a4
871 bbci.l a2, 31, 1f // high bit set indicates masked update
DMakefile.in56 -*l) strip_trailopt 'l'; skip_next=yes;; \
57 -*l?*) strip_trailopt 'l';; \
/hal_xtensa-latest/include/xtensa/
Dcoreasm.h459 bbci.l a0, 31, 1f // branch if called with call4
460 bbsi.l a0, 30, 2f // branch if called with call12
469 bbci.l a0, 31, 1f // branch if called with call4
470 bbsi.l a0, 30, 2f // branch if called with call12
479 bbci.l a0, 31, 1f // branch if called with call4
480 bbsi.l a0, 30, 2f // branch if called with call12
Doverlay_os_asm.h106 bbsi.l \sr1, 15, .Lno // If -1 then we're done
Dcacheattrasm.h188 bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore.h109 #define XCHAL__12(a,b,c,d,e,f,g,h,i,j,k,l, x, ...) x argument
110 #define XCHAL__13(a,b,c,d,e,f,g,h,i,j,k,l,m, x, ...) x argument
111 #define XCHAL__14(a,b,c,d,e,f,g,h,i,j,k,l,m,n, x, ...) x argument
112 #define XCHAL__15(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o, x, ...) x argument
113 #define XCHAL__16(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p, x, ...) x argument
114 #define XCHAL__17(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q, x, ...) x argument
115 #define XCHAL__18(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r, x, ...) x argument
116 #define XCHAL__19(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s, x, ...) x argument
/hal_xtensa-latest/include/
DMakefile.in51 -*l) strip_trailopt 'l'; skip_next=yes;; \
52 -*l?*) strip_trailopt 'l';; \
/hal_xtensa-latest/
DMakefile.in50 -*l) strip_trailopt 'l'; skip_next=yes;; \
51 -*l?*) strip_trailopt 'l';; \