Home
last modified time | relevance | path

Searched refs:XCHAL_VISION_SIMD16 (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h178 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h178 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h178 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h178 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h173 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h207 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h207 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h201 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h176 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h200 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h207 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h206 #define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ macro