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Searched refs:XCHAL_VECBASE_RESET_VADDR (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h385 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h482 #define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h482 #define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h482 #define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h505 #define XCHAL_VECBASE_RESET_VADDR 0x9F180800 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h524 #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h532 #define XCHAL_VECBASE_RESET_VADDR 0x3B6F8400 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h532 #define XCHAL_VECBASE_RESET_VADDR 0x596F8400 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h587 #define XCHAL_VECBASE_RESET_VADDR 0x1FF80800 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h585 #define XCHAL_VECBASE_RESET_VADDR 0xFE000400 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h617 #define XCHAL_VECBASE_RESET_VADDR 0x40000400 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h559 #define XCHAL_VECBASE_RESET_VADDR 0x21170400 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h620 #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h682 #define XCHAL_VECBASE_RESET_VADDR 0x24020400 /* VECBASE reset value */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h697 #define XCHAL_VECBASE_RESET_VADDR 0x00000400 /* VECBASE reset value */ macro