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Searched refs:XCHAL_UNALIGNED_LOAD_EXCEPTION (Results 1 – 16 of 16) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h118 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h200 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h200 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h200 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h200 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h193 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h173 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h173 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h235 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h235 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h228 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h198 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h226 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h235 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h233 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ macro
/hal_xtensa-latest/src/hal/
Dmemcopy.S336 #if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT