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Searched refs:XCHAL_TRAX_MEM_SHAREABLE (Results 1 – 14 of 14) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h560 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h560 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h560 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h583 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h596 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h598 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h598 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h653 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h651 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h677 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h625 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h692 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h748 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h763 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro