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Searched refs:XCHAL_NUM_TIMERS (Results 1 – 19 of 19) sorted by relevance

/hal_xtensa-latest/src/hal/
Dclock.S86 #if XCHAL_NUM_TIMERS > 0
93 #if XCHAL_NUM_TIMERS > 1
100 #if XCHAL_NUM_TIMERS > 2
117 #if XCHAL_NUM_TIMERS > 0
123 #if XCHAL_NUM_TIMERS > 1
129 #if XCHAL_NUM_TIMERS > 2
Dmisc.c165 const unsigned char Xthal_num_ccompare = XCHAL_NUM_TIMERS;
/hal_xtensa-latest/include/xtensa/
Dxtruntime.h217 #if XCHAL_NUM_TIMERS > 0
220 #if XCHAL_NUM_TIMERS > 1
223 #if XCHAL_NUM_TIMERS > 2
226 #if XCHAL_NUM_TIMERS > 3
Dxtruntime-core-state.h99 STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h232 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h334 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h334 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h334 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h357 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h353 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h322 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h322 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h445 #define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h445 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h417 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h349 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h424 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h445 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h460 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ macro