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Searched refs:XCHAL_MPU_BG_CACHEADRDIS (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h599 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h599 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h599 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h622 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h635 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h693 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h693 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h716 #define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h664 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h730 #define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h788 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h803 #define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ macro