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Searched refs:XCHAL_MPU_ALIGN (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h602 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h602 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h602 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h625 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h638 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h696 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h696 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h719 #define XCHAL_MPU_ALIGN 4096 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h667 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h733 #define XCHAL_MPU_ALIGN 4096 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h791 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h806 #define XCHAL_MPU_ALIGN 0 macro
/hal_xtensa-latest/src/hal/
Dmpu.c81 #define CACHE_REGION_THRESHOLD (32 * XCHAL_DCACHE_LINESIZE / XCHAL_MPU_ALIGN)