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Searched refs:XCHAL_MMU_RINGS (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/src/hal/
Dmisc.c107 const unsigned char Xthal_mmu_rings = XCHAL_MMU_RINGS;
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h469 #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h588 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h588 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h588 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h611 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h624 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h625 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h625 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h681 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h681 #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h704 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h653 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h719 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h776 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h791 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h902 …HAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2