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Searched refs:XCHAL_INTLEVEL4_VECTOR_VADDR (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h566 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x3B6F85BC macro
569 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h566 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x596F85BC macro
569 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h621 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x1FF80A00 macro
624 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h619 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000600 macro
622 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h651 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x400005BC macro
654 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h593 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x211705BC macro
596 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h716 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x240205BC macro
719 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h731 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000005BC macro
734 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h419 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h522 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h522 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h522 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h545 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x9F180A00 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h558 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h654 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 macro