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Searched refs:XCHAL_INTLEVEL4_VECTOR_PADDR (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h567 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x3B6F85BC macro
570 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h567 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x596F85BC macro
570 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h622 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x1FF80A00 macro
625 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h620 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000600 macro
623 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h652 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x400005BC macro
655 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h594 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x211705BC macro
597 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h717 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x240205BC macro
720 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h732 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000005BC macro
735 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h420 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h523 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h523 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h523 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h546 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x9F180A00 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h559 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h655 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 macro