Home
last modified time | relevance | path

Searched refs:XCHAL_HAVE_WINDOWED (Results 1 – 19 of 19) sorted by relevance

/hal_xtensa-latest/include/xtensa/
Dcoreasm.h396 #if XCHAL_HAVE_WINDOWED
408 #if XCHAL_HAVE_WINDOWED
420 #if XCHAL_HAVE_WINDOWED
456 #if XCHAL_HAVE_WINDOWED
514 #if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
900 #if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
934 #if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
988 #if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
Dxtruntime-core-state.h52 #if XCHAL_HAVE_WINDOWED
59 #if XCHAL_HAVE_WINDOWED
/hal_xtensa-latest/src/hal/
Dwindowspill_asm.S94 #if ! XCHAL_HAVE_WINDOWED
370 #if XCHAL_HAVE_WINDOWED
Dmisc.c47 const unsigned char Xthal_have_windowed = XCHAL_HAVE_WINDOWED;
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ macro