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Searched refs:XCHAL_HAVE_PRID (Results 1 – 18 of 18) sorted by relevance

/hal_xtensa-latest/src/hal/
Dmp_asm.S116 #if XCHAL_HAVE_PRID
Dmisc.c64 const unsigned char Xthal_have_prid = XCHAL_HAVE_PRID;
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h82 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h85 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h86 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h86 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h83 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h83 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/include/xtensa/
Dcore-macros.h416 #if XCHAL_HAVE_PRID
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h83 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h85 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h84 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h83 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h83 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro