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Searched refs:XCHAL_HAVE_OCD (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h442 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h551 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h551 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h551 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h574 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h587 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h589 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h589 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h644 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h642 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h668 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h616 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h683 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h739 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h754 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ macro