Home
last modified time | relevance | path

Searched refs:XCHAL_HAVE_NMI (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/include/xtensa/
Dxtruntime-core-state.h72 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
73 STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
74 STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
75 STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
/hal_xtensa-latest/src/hal/
Dmisc.c63 const unsigned char Xthal_have_nmi = XCHAL_HAVE_NMI;
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h230 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h332 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h332 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h332 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h355 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h351 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h320 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h320 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h443 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h443 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h415 #define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h347 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h422 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h443 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h458 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ macro