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Searched refs:XCHAL_HAVE_MIMIC_CACHEATTR (Results 1 – 19 of 19) sorted by relevance

/hal_xtensa-latest/include/xtensa/
Dcacheattrasm.h38 #define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEA…
327 # if XCHAL_HAVE_MIMIC_CACHEATTR
363 # if XCHAL_HAVE_MIMIC_CACHEATTR
Dxtruntime-core-state.h138 #if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
/hal_xtensa-latest/src/hal/
Dmisc.c93 const unsigned char Xthal_have_mimic_cacheattr = XCHAL_HAVE_MIMIC_CACHEATTR;
Dcache_asm.S247 #elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_S…
306 #elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h459 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h579 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h579 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h579 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h602 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h615 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h617 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h617 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h672 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h670 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h695 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h644 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h710 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h767 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h782 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ macro