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Searched refs:XCHAL_HAVE_L2_CACHE (Results 1 – 5 of 5) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h328 #define XCHAL_HAVE_L2_CACHE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h328 #define XCHAL_HAVE_L2_CACHE 0 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h321 #define XCHAL_HAVE_L2_CACHE 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h328 #define XCHAL_HAVE_L2_CACHE 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h326 #define XCHAL_HAVE_L2_CACHE 0 macro