| /hal_xtensa-latest/src/hal/ |
| D | int_asm.S | 30 #if XCHAL_HAVE_INTERRUPTS
54 # if XCHAL_HAVE_INTERRUPTS
68 # if XCHAL_HAVE_INTERRUPTS
85 # if XCHAL_HAVE_INTERRUPTS
97 # if XCHAL_HAVE_INTERRUPTS
111 # if XCHAL_HAVE_INTERRUPTS
122 # if XCHAL_HAVE_INTERRUPTS
142 # if XCHAL_HAVE_INTERRUPTS
174 # if XCHAL_HAVE_INTERRUPTS
245 # if XCHAL_HAVE_INTERRUPTS
[all …]
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| D | interrupts.c | 29 #if XCHAL_HAVE_INTERRUPTS
215 #if XCHAL_HAVE_INTERRUPTS
396 #if XCHAL_HAVE_INTERRUPTS in xthal_vpri_to_intlevel()
412 #if XCHAL_HAVE_INTERRUPTS in xthal_intlevel_to_vpri()
428 #if XCHAL_HAVE_INTERRUPTS in xthal_int_enable()
472 #if XCHAL_HAVE_INTERRUPTS in xthal_int_disable()
490 #if XCHAL_HAVE_INTERRUPTS in xthal_set_vpri_locklevel()
504 #if XCHAL_HAVE_INTERRUPTS in xthal_get_vpri_locklevel()
525 #if XCHAL_HAVE_INTERRUPTS in xthal_set_int_vpri()
599 #if XCHAL_HAVE_INTERRUPTS in xthal_get_int_vpri()
[all …]
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| D | mp_asm.S | 81 # if XCHAL_HAVE_INTERRUPTS
90 # if XCHAL_HAVE_INTERRUPTS
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| D | mem_ecc_parity.S | 117 # if XCHAL_HAVE_INTERRUPTS
270 # if XCHAL_HAVE_INTERRUPTS
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| D | misc.c | 61 const unsigned char Xthal_have_interrupts = XCHAL_HAVE_INTERRUPTS;
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| /hal_xtensa-latest/include/xtensa/ |
| D | core-macros.h | 330 #if XCHAL_HAVE_INTERRUPTS
435 #elif XCHAL_HAVE_INTERRUPTS in XTHAL_COMPARE_AND_SET()
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| D | xtruntime.h | 79 #if !XCHAL_HAVE_INTERRUPTS
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| D | xtruntime-core-state.h | 101 #if XCHAL_HAVE_INTERRUPTS
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| D | coreasm.h | 302 #if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
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| /hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/ |
| D | core-isa.h | 228 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/ |
| D | core-isa.h | 330 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/ |
| D | core-isa.h | 330 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/ |
| D | core-isa.h | 330 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/ |
| D | core-isa.h | 353 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/ |
| D | core-isa.h | 349 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/ |
| D | core-isa.h | 318 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/ |
| D | core-isa.h | 318 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/ |
| D | core-isa.h | 442 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/ |
| D | core-isa.h | 442 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/ |
| D | core-isa.h | 414 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/ |
| D | core-isa.h | 345 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/ |
| D | core-isa.h | 421 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/ |
| D | core-isa.h | 442 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/ |
| D | core-isa.h | 457 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ macro
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