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Searched refs:XCHAL_HAVE_DCACHE_TEST (Results 1 – 16 of 16) sorted by relevance

/hal_xtensa-latest/src/hal/
Dmem_ecc_parity.S165 # if XCHAL_DCACHE_SIZE && XCHAL_HAVE_DCACHE_TEST
Dcache_asm.S60 && XCHAL_HAVE_DCACHE_TEST && XCHAL_HAVE_MINMAX && XCHAL_HAVE_LOOPS
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h257 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h257 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h257 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h257 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h250 #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h230 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h230 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h312 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h312 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h305 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h255 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h300 #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h312 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h310 #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ macro