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Searched refs:XCHAL_HAVE_CP (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/src/hal/
Dstate_asm.S278 #if XCHAL_HAVE_CP
296 #if XCHAL_HAVE_CP
319 #if XCHAL_HAVE_CP
340 #if XCHAL_HAVE_CP
/hal_xtensa-latest/include/xtensa/
Dxtruntime-core-state.h133 #if XCHAL_HAVE_CP
176 #if XCHAL_HAVE_CP
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h88 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h97 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h95 #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h96 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h96 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h95 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h94 #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h93 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ macro