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Searched refs:XCHAL_HAVE_ACELITE (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h279 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h279 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h279 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h279 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h272 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h357 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h357 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h350 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h277 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h336 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h357 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h355 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro