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Searched refs:XCHAL_DCACHE_SIZE (Results 1 – 22 of 22) sorted by relevance

/hal_xtensa-latest/include/xtensa/
Dcacheasm.h481 #if XCHAL_DCACHE_SIZE > 0
591 #if XCHAL_DCACHE_SIZE > 0
609 #if XCHAL_DCACHE_SIZE > 0
626 #if XCHAL_DCACHE_SIZE > 0
628 …cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loop…
645 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
661 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
677 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
679 cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
696 #if XCHAL_DCACHE_SIZE > 0
[all …]
Dcore-macros.h139 #if XCHAL_DCACHE_SIZE > 0
165 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
177 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
189 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
204 unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
205 XCHAL_DCACHE_SIZE : _s; \
212 if (max <= XCHAL_DCACHE_SIZE) { \
293 #if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
/hal_xtensa-latest/src/hal/
Dcache.c47 const unsigned int Xthal_dcache_size = XCHAL_DCACHE_SIZE;
Dcache_asm.S59 #if (!defined(XCHAL_HAVE_NX) || XCHAL_HAVE_NX == 0) && XCHAL_DCACHE_SIZE > 0 \
61 movi a4, XCHAL_DCACHE_SIZE*2 // size at which to use huge algorithm
72 movi a7, XCHAL_DCACHE_SIZE/XCHAL_DCACHE_LINESIZE // a7 = number of lines in dcache
73 movi a3, XCHAL_DCACHE_SIZE-XCHAL_DCACHE_LINESIZE // way index
76 movi a10, (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) - 1
Dmem_ecc_parity.S160 # if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE
165 # if XCHAL_DCACHE_SIZE && XCHAL_HAVE_DCACHE_TEST
Dset_region_translate.c452 #if ((XCHAL_DCACHE_SIZE >0) && XCHAL_DCACHE_IS_WRITEBACK) in xthal_set_region_translation()
486 # if XCHAL_DCACHE_SIZE > 0 in xthal_set_region_translation()
Dattribute.c231 # if XCHAL_ICACHE_SIZE == 0 && XCHAL_DCACHE_SIZE == 0 in xthal_set_region_attribute()
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h163 #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h245 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h245 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h245 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h245 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h238 #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h218 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h218 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h298 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h298 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h291 #define XCHAL_DCACHE_SIZE 131072 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h243 #define XCHAL_DCACHE_SIZE 65536 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h286 #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h298 #define XCHAL_DCACHE_SIZE 65536 /* D-cache size in bytes or 0 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h296 #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ macro