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Searched refs:XCHAL_DCACHE_ACCESS_SIZE (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h204 #define XCHAL_DCACHE_ACCESS_SIZE 4 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h302 #define XCHAL_DCACHE_ACCESS_SIZE 8 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h302 #define XCHAL_DCACHE_ACCESS_SIZE 8 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h302 #define XCHAL_DCACHE_ACCESS_SIZE 8 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h302 #define XCHAL_DCACHE_ACCESS_SIZE 8 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h295 #define XCHAL_DCACHE_ACCESS_SIZE 1 macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h272 #define XCHAL_DCACHE_ACCESS_SIZE 16 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h272 #define XCHAL_DCACHE_ACCESS_SIZE 16 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h384 #define XCHAL_DCACHE_ACCESS_SIZE 16 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h384 #define XCHAL_DCACHE_ACCESS_SIZE 16 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h377 #define XCHAL_DCACHE_ACCESS_SIZE 8 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h300 #define XCHAL_DCACHE_ACCESS_SIZE 16 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h363 #define XCHAL_DCACHE_ACCESS_SIZE 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h382 #define XCHAL_DCACHE_ACCESS_SIZE 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h384 #define XCHAL_DCACHE_ACCESS_SIZE 16 macro