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Searched refs:XCHAL_CP_PORT_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
Dcore.h991 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
1039 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
1113 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dtie.h38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dtie.h38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dtie.h38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dtie.h38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h1087 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
1135 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
1196 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)