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Searched refs:XCHAL_CP_MASK (Results 1 – 19 of 19) sorted by relevance

/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ macro
Dcore.h991 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
1039 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
1113 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
1224 #if XCHAL_CP_MASK == 0
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dtie.h37 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dtie.h37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/include/xtensa/
Dxtruntime-frames.h119 #if (XCHAL_CP_MASK & CP0_MASK)
122 #if (XCHAL_CP_MASK & CP1_MASK)
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/src/hal/
Dstate.c94 const unsigned int Xthal_cp_mask = XCHAL_CP_MASK;
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h37 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dtie.h37 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dtie.h37 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */ macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h1087 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
1135 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
1196 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
1294 #if XCHAL_CP_MASK == 0