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Searched refs:XCHAL_CP3_SA_SIZE (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/include/xtensa/
Dxtruntime-core-state.h186 #if XCHAL_CP3_SA_SIZE > 0
187 STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/src/hal/
Dstate.c43 XCHAL_CP3_SA_SIZE,
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h52 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dtie.h52 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dtie.h54 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dtie.h52 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h57 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h57 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h57 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h1100 # if XCHAL_CP3_SA_SIZE == 0
1154 # if XCHAL_CP3_SA_SIZE
1215 # if XCHAL_CP3_SA_SIZE
1302 #define XCHAL_CP3_SA_SIZE 0 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore.h1004 # if XCHAL_CP3_SA_SIZE == 0
1064 # if XCHAL_CP3_SA_SIZE
1138 # if XCHAL_CP3_SA_SIZE
1232 #define XCHAL_CP3_SA_SIZE 0 macro