Home
last modified time | relevance | path

Searched refs:XCHAL_CP2_SA_ALIGN (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/src/hal/
Dstate.c54 XCHAL_CP2_SA_ALIGN,
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h51 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dtie.h51 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dtie.h53 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dtie.h51 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h56 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h56 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h56 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/include/xtensa/
Dxtruntime-core-state.h184 STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
/hal_xtensa-latest/include/xtensa/config/
Dcore.h1301 #define XCHAL_CP2_SA_ALIGN 1 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore.h1231 #define XCHAL_CP2_SA_ALIGN 1 macro