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Searched refs:XTHAL_TIMER_UNCONFIGURED (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h525 #define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED
526 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
527 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h438 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
439 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h438 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
439 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/include/xtensa/
Dhal.h479 #define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ macro
480 #define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */
/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h428 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h428 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h428 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h449 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h451 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h487 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED