Home
last modified time | relevance | path

Searched refs:XCHAL_INT18_LEVEL (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h380 #define XCHAL_INT18_LEVEL 5 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h380 #define XCHAL_INT18_LEVEL 5 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h380 #define XCHAL_INT18_LEVEL 5 macro
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h399 #define XCHAL_INT18_LEVEL 1 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h403 #define XCHAL_INT18_LEVEL 5 macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h368 #define XCHAL_INT18_LEVEL 2 macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h368 #define XCHAL_INT18_LEVEL 2 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h433 #define XCHAL_INT18_LEVEL 5 macro
/hal_xtensa-3.4.0/src/hal/
Dinterrupts.c327 DEFAULT_INTVPRI( XCHAL_INT18_LEVEL ),
/hal_xtensa-3.4.0/include/xtensa/config/
Dcore.h262 XCHAL_SEP XCHAL_INT18_LEVEL \
412 # define XCHAL_INT18_LEVEL 0 macro