Searched refs:XCHAL_ICACHE_LINESIZE (Results 1 – 15 of 15) sorted by relevance
| /hal_xtensa-3.4.0/src/hal/ |
| D | cache.c | 34 const unsigned short Xthal_icache_linesize = XCHAL_ICACHE_LINESIZE;
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| D | mem_ecc_parity.S | 62 # define CACHE_LINESIZE_MIN XCHAL_ICACHE_LINESIZE
198 addi a3, a3, XCHAL_ICACHE_LINESIZE-1
207 addi a2, a2, XCHAL_ICACHE_LINESIZE // increment to next line
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| D | cache_asm.S | 135 movi a7, -XCHAL_ICACHE_LINESIZE // for rounding to cache line size
139 addi a5, a5, XCHAL_ICACHE_LINESIZE-1
141 movi a7, XCHAL_ICACHE_SIZE/XCHAL_ICACHE_LINESIZE // a7 = number of lines in dcache
142 movi a3, XCHAL_ICACHE_SIZE-XCHAL_ICACHE_LINESIZE // way index
153 addi a3, a3, -XCHAL_ICACHE_LINESIZE
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| /hal_xtensa-3.4.0/include/xtensa/ |
| D | cacheattrasm.h | 401 # if XCHAL_ICACHE_LINESIZE < 4
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| D | cacheasm.h | 354 …cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loop…
443 cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
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| /hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/ |
| D | core-isa.h | 239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/ |
| D | core-isa.h | 239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/ |
| D | core-isa.h | 239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/ |
| D | core-isa.h | 232 #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/ |
| D | core-isa.h | 239 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/ |
| D | core-isa.h | 291 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/ |
| D | core-isa.h | 212 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/ |
| D | core-isa.h | 212 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/ |
| D | core-isa.h | 264 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
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| /hal_xtensa-3.4.0/include/xtensa/config/ |
| D | core.h | 778 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
780 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE
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