Home
last modified time | relevance | path

Searched refs:XCHAL_HAVE_PRID (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.4.0/src/hal/
Dmp_asm.S116 #if XCHAL_HAVE_PRID
Dmisc.c64 const unsigned char Xthal_have_prid = XCHAL_HAVE_PRID;
/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h85 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h87 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h83 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h86 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h86 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h84 #define XCHAL_HAVE_PRID 1 /* processor ID register */ macro
/hal_xtensa-3.4.0/include/xtensa/
Dcore-macros.h416 #if XCHAL_HAVE_PRID