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Searched refs:XCHAL_DCACHE_SETWIDTH (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.4.0/src/hal/
Dcache.c39 const unsigned char Xthal_dcache_setwidth = XCHAL_DCACHE_SETWIDTH;
/hal_xtensa-3.4.0/include/xtensa/
Dcacheasm.h937 slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
938 slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h288 #define XCHAL_DCACHE_SETWIDTH 8 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h288 #define XCHAL_DCACHE_SETWIDTH 8 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h288 #define XCHAL_DCACHE_SETWIDTH 8 macro
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h281 #define XCHAL_DCACHE_SETWIDTH 0 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h288 #define XCHAL_DCACHE_SETWIDTH 8 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h366 #define XCHAL_DCACHE_SETWIDTH 8 macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h258 #define XCHAL_DCACHE_SETWIDTH 7 macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h258 #define XCHAL_DCACHE_SETWIDTH 7 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h330 #define XCHAL_DCACHE_SETWIDTH 8 macro
/hal_xtensa-3.4.0/include/xtensa/config/
Dcore.h787 #define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH)
789 #if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
793 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH