Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 – 13 of 13) sorted by relevance
| /hal_xtensa-3.4.0/src/hal/ |
| D | mem_ecc_parity.S | 60 #if XCHAL_ICACHE_LINEWIDTH < XCHAL_DCACHE_LINEWIDTH && XCHAL_ICACHE_SIZE > 0
64 # define CACHE_LINEWIDTH_MIN XCHAL_DCACHE_LINEWIDTH
170 extui a9, a2, 0, XCHAL_DCACHE_LINEWIDTH
174 srli a3, a3, XCHAL_DCACHE_LINEWIDTH // size in cache lines
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| D | cache.c | 31 const unsigned char Xthal_dcache_linewidth = XCHAL_DCACHE_LINEWIDTH;
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| /hal_xtensa-3.4.0/include/xtensa/ |
| D | cacheasm.h | 611 cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
663 cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
714 cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
772 cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
808 cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
937 slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
938 slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
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| /hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/ |
| D | core-isa.h | 242 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/ |
| D | core-isa.h | 242 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/ |
| D | core-isa.h | 242 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/ |
| D | core-isa.h | 235 #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/ |
| D | core-isa.h | 242 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/ |
| D | core-isa.h | 294 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/ |
| D | core-isa.h | 215 #define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/ |
| D | core-isa.h | 215 #define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/ |
| D | core-isa.h | 267 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
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| /hal_xtensa-3.4.0/include/xtensa/config/ |
| D | core.h | 782 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH
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