Home
last modified time | relevance | path

Searched refs:XCHAL_CP2_SA_SIZE (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.4.0/include/xtensa/
Dxtruntime-core-state.h183 #if XCHAL_CP2_SA_SIZE > 0
184 STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h52 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/src/hal/
Dstate.c42 XCHAL_CP2_SA_SIZE,
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h52 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h50 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dtie.h50 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h55 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h55 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h55 #define XCHAL_CP2_SA_SIZE 0 macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dtie.h56 #define XCHAL_CP2_SA_SIZE 0
/hal_xtensa-3.4.0/include/xtensa/config/
Dcore.h1096 # if XCHAL_CP2_SA_SIZE == 0
1148 # if XCHAL_CP2_SA_SIZE
1209 # if XCHAL_CP2_SA_SIZE
1300 #define XCHAL_CP2_SA_SIZE 0 macro