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Searched refs:XCHAL_CP1_SA_SIZE (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.4.0/include/xtensa/
Dxtruntime-core-state.h180 #if XCHAL_CP1_SA_SIZE > 0
181 STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
Dxtruntime-frames.h123 STRUCT_AFIELD (long,4,UEXC_,cp1, XCHAL_CP1_SA_SIZE / 4)
126 #define ALIGNPAD ((2 + XCHAL_HAVE_MAC16*2 + ((XCHAL_CP0_SA_SIZE%16)/4) + ((XCHAL_CP1_SA_SIZE%16)/4…
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h45 #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ macro
/hal_xtensa-3.4.0/src/hal/
Dstate.c41 XCHAL_CP1_SA_SIZE,
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h45 #define XCHAL_CP1_SA_SIZE 208 /* size of state save area */ macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h43 #define XCHAL_CP1_SA_SIZE 208 /* size of state save area */ macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dtie.h43 #define XCHAL_CP1_SA_SIZE 208 /* size of state save area */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h50 #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h50 #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h50 #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dtie.h51 #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */
/hal_xtensa-3.4.0/include/xtensa/config/
Dcore.h1092 # if XCHAL_CP1_SA_SIZE == 0
1142 # if XCHAL_CP1_SA_SIZE
1203 # if XCHAL_CP1_SA_SIZE
1298 #define XCHAL_CP1_SA_SIZE 0 macro