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Searched refs:XCHAL_CLOCK_GATING_GLOBAL (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-3.4.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h197 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h197 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h197 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h190 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h197 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h232 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h170 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h170 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/zephyr/soc/intel_s1000/xtensa/config/
Dcore-isa.h214 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ macro
/hal_xtensa-3.4.0/include/xtensa/config/
Dcore.h109 XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) )